The present invention relates to the compression of signal samples generated by parallel, time-interleaved analog to digital (A/D) converters and to the subsequent decompression of the compressed samples.
Parallel, time-interleaved analog to digital converters (TIADCs) are well known by those skilled the art as being useful for high speed data conversion of analog signals. TIADCs are used to sample analog signals at high sample rates, usually above 100 Msamp/sec. A TIADC can sample an analog signal at a sample rate fs that is a multiple of the sample rate fsADC of a single analog to digital converter (ADC). In general, a TIADC device includes two or more individual analog to digital converters operating in parallel at the same sample rate, with each ADC sampling at a different phase offset. The resulting samples from the parallel ADCs are consecutive and have a fixed time delay between samples corresponding to the phase offset. For example, for N parallel ADCs each operating at a sample rate of fsADC the delay between consecutive samples the TIADC is Ts=1/(NfsADC). The sample rate of signal samples at the output of the TIADC is fs=1/Ts. Architectures for TIADCs are described by Miki et al. in U.S. Pat. No. 4,968,988 and by El-Sankary et al. in “A New Time-Interleaved Architecture for High-Speed A/D Converters”, IEEE International Workshop on Digital and Computational Video, November 2002, pp. 93-99, both incorporated herein by reference. There are many different implementations of TIADCs well known to those skilled in the art.
In many high-speed applications, signal samples thus generated have a fixed data width, such as 12 bits per sample, and are stored in memory and/or transferred over a data bus, network connection or other interface. Data transfers, especially over legacy interfaces, may not be able to keep up with data output from the TIADC, thus creating bottlenecks and large memory requirements. As data converter technology improves and sample rate and bit width per sample increase, the problems of transferring sampled data streams over standard busses or networks and storing sampled data in semiconductor memory or on disks become worse. These problems are made N times more difficult when the sampled data are generated by N parallel time interleaved ADCs. Compression of samples output from TIADCs reduces bandwidth requirements (sample widths and/or clock rates) and thus reduces required storage capacity, increases the speed and/or reduces the time required to transfer sampled data over an interface.
In the context of the present invention, the term “high-speed signals” refers generally to signals whose bandwidth of 50 MHz or higher requires sample rates of 100 megasamples/sec (Msamp/sec) or higher. Such high-speed signals become more prevalent every year because the operating frequencies, or clock rates, of electronic components continue to increase according to Moore's Law, which states that the density of transistors in semiconductor devices will double every 18 months. As the transistors become smaller, their switching speeds increase proportionally; smaller transistors switch at faster rates. As higher transistor switching speeds enable faster operating frequencies for electronic components, signals with wider bandwidths can be processed, because faster transistors are used to build faster A/D and D/A converters, especially using CMOS technology.
To provide an example of increasing signal bandwidths and ADC sample rates over time, cellular telephony began in the 1980s with an analog bandwidth per channel of just 30 kHz, and all of the processing was performed using analog technology. In the 1990s, the Global System for Mobility (GSM) cellular standard deployed 200 KHz carriers, for a 7 times increase in bandwidth over the earlier analog cellular bandwidth. GSM processing was performed using a combination of analog filtering of these 200 KHz carriers, followed by ADC sampling of the filtered signal and subsequent digital processing by digital signal processor (DSP) chips. The so-called 3G wireless standard that began to be deployed in 2002 uses 5 MHz carriers, and the emerging (as of 2006) WiMax standard uses up to 40 MHz carrier bandwidth. These 3G and WiMax systems utilize A/D and D/A converters operating at tens and hundreds of Msamp/sec to digitize multiple carriers at once, performing all filtering and subsequent processing in the digital domain. These trends towards wider signal bandwidths are also prevalent in medical imaging (including computed tomography [CT] scanners, ultrasound, and magnetic resonance imaging [MRI]) and test and measurement equipment (including oscilloscopes and waveform generators), among other application areas.
Test and measurement equipment is an important application because every electronic device must be tested, both during the development stage and in the production stage. Such testing is commonly performed by oscilloscopes, which display a visual representation of an electronic waveform whose characteristics are then measured. As the switching speeds of transistors increases, oscilloscopes keep up by increasing the sample rate of their front end A/D converters. Given the architectural and process limitations of the fastest available A/D converter architecture, flash A/D converters, the maximum rate of a single flash A/D converter is today (2006) on the order of 1 Gsamp/sec, using 8-bit samples. If a signal with a bandwidth above 500 MHz (the Nyquist frequency when the sample rate is 1 Gsamp/sec) is to be digitized, multiple, time-interleaved A/D converters operating in parallel will have to be employed. As is well known to those skilled in the art of oscilloscopes, a high oversampling ratio of at least 5×, and preferably 10×, of the input signal bandwidth, is desirable in order to make accurate measurements of common signal parameters such as rise time, fall time, jitter, and signal period. Thus for the fastest electronic signals, such as 6.25 Gbps serializer/deserializer (SerDes) waveforms, an oscilloscope's sample rate should be at least 6.25×5x=31.25 Gsamp/sec, and preferably 6.25×10x=62.5 Gsamp/sec. Since the maximum sample rate of the fastest single A/D converters (flash A/D converters) is limited to about 1 Gsamp/sec, the oscilloscope sample rates required to measure such wideband signals can only be achieved using TIADCs. The present invention improves the operation of such TIADCs by providing compression as described below.
When purchasing an oscilloscope, there are two primary figures of merit that matter: scope bandwidth and scope memory depth. As discussed above, faster signaling rates require wider scope bandwidth and a correspondingly faster oscilloscope A/D converter front end. The second parameter, memory depth, also increases every year for a related reason. If a fixed time duration, such as 1 microsecond (usec), of a signal is to be captured in an oscilloscope, the amount of memory used to capture the A/D converter samples corresponding to that time duration is proportional to the sample rate. If the sample rate doubles, the amount of memory needed to capture the signal also doubles, though the signal duration remains constant. For instance, at 20 Gsamp/sec, a 1 usec signal capture generates 20,000 samples. At 40 Gsamp/sec, a 1 usec signal capture generates 40,000 samples. So simply by requiring faster A/D converter front ends year after year, an oscilloscope's sample memory must also be increased each year. Furthermore, the oscilloscope sample capture memory must be designed to accept the higher-rate samples, and that is not always easily achieved. For example, the fastest available memory technology (SRAM) is often used to capture oscilloscope samples, but SRAM cells are typically limited to 500 MHz clock rates for sequential accesses. In order to capture A/D converter samples at 40 Gsamp/sec, an interleaving or demultiplexing strategy reduces the raw A/D converter rate to a rate that can be used with conventional SRAM cells. Thus a 40 Gsamp/sec front end must be demultiplexed into at least 80 streams, each of which accesses an SRAM block at 500 Msamp/sec. As oscilloscope sample rates increase year after year, these demultiplexing and interleaving strategies increase the complexity and cost of oscilloscope storage subsystems.
An oscilloscope's memory subsystem is often the most expensive portion of the application specific integrated circuit (ASIC) that implements its TIADC and capture memory.
In order to achieve the highest sample rates in combination with deep memory for capturing those high-speed samples, oscilloscope manufacturers such as Agilent and Tektronix have designed their own ASICs that combine TIADCs with capture memory subsystems on a single IC. It is important to note that these custom oscilloscope ASICs dedicate most of the chip area (gate count) to the memory subsystem, not to TIADC subsystem. Thus from a cost perspective, the high-speed capture memory is the significantly more expensive element of the front-end oscilloscope ASIC. Because the present invention's compression technology enables the storage of significantly more samples, in compressed form, in an oscilloscope's high-speed capture memory, the present invention significantly lowers the cost per bit of one of the most expensive (and most visible, from a marketing perspective) components of a high-speed digital storage oscilloscope (DSO). To summarize, the present invention enables a significant increase in the signal duration that can be captured and stored in data acquisition systems, such as those found in DSOs, by compressing the samples after acquisition by a TIADC front end and prior to storing or transmitting the compressed samples in a capture memory (such as in high-speed SRAM in a DSO).
In U.S. Pat. No. 5,973,629, Fujii describes compression of signal samples output from a single ADC. Fujii teaches differential encoding of samples by applying a delay to each sample to form a previous sample and subtracting the previous sample from a current sample to form a difference sample. Variable quantization is then applied to the difference samples to form an output bit stream. Fujii's system uses a single ADC so that a delay element is required to form differences between consecutive signal samples. In U.S. Pat. No. 5,127,022, Takegahara describes differential encoding of signal samples output from a single ADC. Takegahara teaches applying one or more delays to output samples so that the differences formed are between samples separated by one or more sampling intervals. A selector selects the delay(s) that produces the lower magnitude difference signal. Takegahara's system uses a single ADC so that one or more delay elements are required for differential encoding.
In U.S. Pat. No. 6,476,749 B1, Yeap et al. describe a TIADC system wherein the analog signal is channelized and each channel is input to a different ADC. Subsequent to sampling, the signal samples output from each ADC are summed to produce a full bandwidth sampled signal. Yeap et al. do not teach compression of the samples output from the TIADCs.
In U.S. Pat. No. 4,982,193, Saul et al. describe a TIADC system wherein an analog signal is sampled at multiples of a carrier frequency of the analog signal. Samples that correspond with the same carrier phase, output from the same ADC, are averaged in order to improve the signal-to-noise ratio. Saul et al. do not teach compression of the samples output from the TIADCs.
In U.S. Patent Application Publication no. US2003/0076899 A1, Kumar et al. describe a TIADC system wherein the parallel ADCs are followed by a polyphase filter bank and an FFT processor. Kumar's system samples as well as channelizes an input analog signal. Kumar et al. do not teach compression of the signal samples output from the TIADCs.
In summary, above cited patents '629 and '022 disclose forms of differential encoding applied to samples output from a single ADC. Because there is a single ADC, the differential encoding disclosed requires at least one delay element to delay each output sample from the ADC in order form a difference with each current sample. The above cited patents '749 and '193 and patent application '899 disclose various operations on the signal samples output from TIADCs for various purposes. They do not disclose differential encoding or other compression of the signal samples output from the TIADC.